gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: august 1997 document no. 521 - 33 - 04 data sheet features ? 4:2:2 to over-sampled rgb or yc b c r conversion in a single device ? single 10 bit 4:2:2 input ? internal 4:2:2 de-multiplexer ? 4:2:2 to 8:8:8 interpolation filters ? internal yc b cr to rg b color space conversion ? optional yc b c r (8:8:8) output mode ? setup insertion in luminance channel under user control ? user selectable digital sin x/x correction ? rounding to 10/8 bit resolution per output channel ? 40 mhz maximum clock rate ? single +5 v power supply applications ? over-sampling 4:2:2 to analog rgb conversions for video monitoring ? over-sampling 4:2:2 to analog ycbcr conversions for video monitoring device description the GF9103 is specifically designed to simplify conversions from 4:2:2 component digital video to analog rgb or analog yc b c r component video. the GF9103 simplifies this process by performing 4:2:2 to 8:8:8 interpolation, digital color space conversion and digital sin x/x correction in a single device. immediately following the GF9103, three over-sampled channels of rgb or yc b c r data may be passed through digital to analog converters and simplified analog reconstruction filters. the GF9103 accepts a single 10 bit stream of 4:2:2 data and internally de-multiplexes it into three 10 bit channels of yc b c r data. the yc b c r data is then passed through three linear phase fir filters that over-sample the y data by a factor of 2 and the c b and c r data by a factor of 4. while operating in an over-sampled rgb output mode, the interpolated yc b c r data is passed through the internal color space converter to convert the yc b c r data to rgb data according to ccir-601. alternatively, the color space converter may be bypassed to obtain over-sampled yc b c r (8:8:8) output data. while operating in yc b c r output mode, setup may be dynamically inserted into the luminance channel. prior to output rounding, over-sampled yc b c r or rgb data may be corrected for sin x/x characteristics of d/a conversion. output data may be rounded to 10 or 8 bit resolution per channel. c b and c r may be presented as signed or unsigned data. the GF9103 is packaged in a 68 pin plcc package, operates with a single +5 v power supply and typically consumes only 85 ma of current when operated at 27 mhz. functional block diagram ordering information part number package temperature range GF9103-cps 68 pin plcc 0 to 70 c GF9103-cts 68 pin plcc tape 0 to 70 c 10 10 10 clip & round clip & round clip & round select_matrix setup setup sin x/x sin x/x sin x/x y multiplexed 4:2:2 data stream in ycbcr to rgb matrix bypass cb 4:2:2 demux sync clk oe cr y x2 x4 x4 cb cr cr y cb y/g cr/r cb/b y/g cb/b cr/r y/g cb/b cr/r y/g cb/b cr/r cb/b cr/r 2's comp convert 2's comp 10 multi gen ? GF9103 over-sampling color space converter for video monitoring
521 - 33 - 04 2 pin description pin no. symbol description 10, 18, 27, 36, 44, 52, 61, 68 v dd 5 v 5% power supply. 1, 6, 7, 9, 26, 30, 35, 40, 43, 60, 64 gnd ground. 3 scan_en set low. 8, 11-17, 19, 20 si 9..0 input data port: input data port with internal pull-downs. input data is assumed to be a multiplexed stream of c b yc r [y] c b ..., where [y] denotes an isolated luminance sample. si 9 is the most significant bit and si 0 is the least significant bit. 4oe output enable: active low input with internal pull-up. when oe is high, the output data ports are in high impedance state. 59-53, 51-49 soa 9..0 output data port a: depending on device configuration, soa 9..0 may output over-sampled y or g video. soa 9 is the most significant bit and soa 0 is the least significant bit. 48-45, 42, 41, 39-37, 34 sob 9..0 output data port b: depending on device configuration, sob 9..0 may output over-sampled c b or b video. sob 9 is the most significant bit and sob 0 is the least significant bit. 33-31, 29, 28, 25-21 soc 9..0 output data port c: depending on device configuration, soc 9..0 may output over-sampled c r or r video. soc 9 is the most significant bit and soc 0 is the least significant bit. 2 clk system clock: all timing information relative to rising edge of clock. 5 sync synchronization: control signal input with internal pull-up. this input is used to synchronize the incoming data by holding sync high on clock period n and low on clock period n+1 when the first c b sample is presented to the si 9..0 inputs. sync may be held low until re- synchronization is desired or may be toggled at every occurrence of a c b sample. 65 select_matrix select color space conversion: control signal input with internal pull-down. select_matrix is used to enable and disable the internal yc b c r to rgb color space converter. color space conversion is enabled while select_matrix is high and is disabled while select_matrix is low. 66 bypass bypass sin x/x correction: control signal input with internal pull-up. when bypass is high, sin x/x correction for the three output channels is enabled. while bypass is low, sin x/x correction is by-passed. 63 setup setup: control signal input with internal pull-down. setup is used to enable and disable setup insertion in the luminance channel. 62 convert two's complement conversion: control signal input with internal pull-up. while convert is high, sob 9..0 and soc 9..0 output signed (twos complement) digital data. while convert is low, sob 9..0 and soc 9..0 output unsigned (offset binary) data. when operating in rgb output mode, the convert pin is over-ridden and both sob 9..0 and soc 9..0 output unsigned digital data. soa 9..0 outputs unsigned digital data in all operating modes. 67 rnd10/8 output rounding: control signal input with internal pull-up. rnd10/8 selects rounding to 10 bit resolution per channel when high and rounding to 8 bit resolution per channel when low.
521 - 33 - 04 3 fig. 1 GF9103 pin connections fig. 2a equivalent input circuit fig. 2b equivalent output circuit gnd soa9 soa8 soa7 soa6 soa5 soa4 soa3 vdd soa2 soa1 soa0 sob9 sob8 sob7 sob6 vdd vdd si8 si7 si6 si5 si4 si3 si2 vdd si1 si0 soc0 soc1 soc2 soc3 soc4 gnd vdd soc5 soc6 gnd soc7 soc8 soc9 sob0 gnd vdd sob1 sob2 sob3 gnd sob4 sob5 gnd gnd si9 gnd gnd sync oe scan_en clk gnd vdd rnd10/8 bypass select_matrix gnd setup convert vdd GF9103 top view 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 n substrate control input p well gnd n p v dd d1 d2 n+ p+ d1 d2 gnd n substrate p well n p n+ p+ v dd
521 - 33 - 04 4 device description the GF9103 is composed of five main sections: 1. 4:2:2 de-multiplexer 2. fir filtering and setup insertion 3. color space conversion 4. digital sin x/x correction 5. output processing 4:2:2 de-multiplexer the de-multiplexer accepts data multiplexed in a smpte 125m compliant format from the si 9..0 input data port. si 9 is the most significant bit and si 0 is the least significant bit. the input data stream is assumed to be a multiplexed stream of c b y c r [y] c b ..., where the three words c b y c r refer to cosited samples and where [y] refers to an isolated luminance sample. when operating the GF9103 with 8 bit input data, si 9..2 should be used to present data to the device and si 1..0 should be set low. at least once during a power cycle, the GF9103 must be synchronized to the incoming data stream. the GF9103 is synchronized by holding sync high on clock period n and low on clock period n+1 when the first c b sample is presented to the si 9..0 inputs. sync may be held low until re-synchronization is desired, or it may be toggled at every occurrence of a c b sample. refer to the timing diagram in figure 9 for required operation of the sync control signal. the internal de-multiplexer will de-multiplex all data in the input data stream including any ancillary, edh,vitc, and eav/sav ... signals that may be present. since this data is passed directly to the interpolation filters in the same way that active video would be, it is recommended that such data be replaced with appropriate blanking levels prior to entering the GF9103. the output of the 4:2:2 de-multiplexer consists of three 10 bit channels of yc b c r data. all three channels are then fed to their respective interpolation filter. interpolation filters within the interpolation stage, the luminance data is over- sampled by a factor of two and the c b and c r data is over- sampled by a factor of four so that the 4:2:2 data is converted to 8:8:8 data. by over-sampling the 4:2:2 data to 8:8:8 data, the size, cost and complexity of the analog reconstruction filters following digital to analog converters are reduced. the luminance data is over-sampled by a linear phase fir filter providing 0.0 db dc gain, +0.038/-0.025 pass- band ripple [0.0 ?s to 0.21 ?s], 6 db attenuation at ?s/4, and 47 db stopband attenuation [0.30 ?s to 0.50 ?s]. figure 3 and figure 4 present the frequency response of the luminance interpolation filter. the c b and c r data is over-sampled by a linear phase fir filter providing 0.0 db dc gain, passband ripple of +0.2 db/- 0.2 db [0.0 to 0.07 ?s], 6 db attenuation at ?s/8 and a stopband attenuation of 28 db [ 0.17?s to 0.50 ?s]. figure 5 and figure 6 present the frequency response of the c b and c r interpolation filters. following the interpolation process, a dc offset may be introduced into the luminance channel. setup insertion is enabled and disabled by the setup control signal. while setup is high, the luminance data is scaled by a factor of +947/1024 and an offset of +71 (decimal) is added. while setup is low, no scaling or offset is applied and the data passes through the stage unmodified. the timing diagram in figure 10 demonstrates the operation of the setup control signal. color space conversion two operating modes exist for the color space converter section. these two modes are controlled by the select_matrix control signal. while select_matrix is low, the de-matrixing 3 x 3 multiplier is bypassed so that over-sampled y c b c r data is passed through the stage unmodified. while select_matrix is high, the 3 x 3 multiplier implements the following color space conversion: sin x/x correction while bypass is high, sin x/x correction is enabled on each of the three output channels. sin x/x correction is implemented by passing the data through a fir filter with the frequency response shown in figure 7. while bypass is low, the fir filter is bypassed and each channel is passed directly to the output processing section. total latency through the device is 22 clock cycles when bypass is low and 24 clock cycles when bypass is high. output processing output data may be rounded to 10 or 8 bit accuracy. rnd10/8 should be set high for 10 bit output rounding and set low for 8 bit output rounding. rounding to 8 bit accuracy is accomplished by adding a rounding bit to so 1 and then zeroing both so 0 and so 1 . c b and c r data may be output as signed (twos complement) or unsigned (offset binary) data depending on the state of the convert control signal. when convert is set high, the c b and c r channels are output as signed (twos complement) data. when convert is set low, c b and c r are output as unsigned (offset binary) data, obtained by inverting the sign bit of the two's complement number. when operating in rgb output mode, the convert pin is over-ridden and rgb data is always output as unsigned (offset binary) data. g b r 1 -689/2048 -1430/2048 1 3548/2048 0 1 0 2807/2048 y c b c r =
521 - 33 - 04 5 control signal/operating mode summary sync the sync control signal provides synchronization for the internal 4:2:2 de-multiplexer. sync should be held high on clock period n and low on clock period n+1 when the first c b sample is presented to the si 9..0 inputs. sync may be held low until re-synchronization is desired or may be toggled at every occurrence of a c b sample. select_matrix and setup select_matrix and setup select the color space conversion and offset insertions which the GF9103 is to perform. the following chart presents the available color space conversions and the corresponding states of the select_matrix and setup control pins. setup is a dynamic pin that may be modified every clock cycle. select_matrix setup description 00 selects output to be over-sampled yc b c r with no setup in y channel. 01 selects output to be over-sampled yc b c r with a scaling factor of +947/1024 and an offset of +71 (decimal) applied to the y channel. 1 x selects output to be over-sampled rgb with no setup. sin x/x correction bypass description 1 sin x/x correction enabled on all output data channels. latency through the device is 24 clock cycles. 0 sin x/x correction disabled. latency through the device is 22 clock cycles. output rounding rnd10/8 description 1 output data rounded to 10 bit resolution per channel. 0 output data rounded to 8 bit resolution per channel. twos complement output conversion convert select_matrix description 10sob 9..0 and soc 9..0 output signed (two's complement) c b and c r data. 00sob 9..0 and soc 9..0 output unsigned (offset binary) c b and c r data. x1sob 9..0 and soc 9..0 output unsigned b and r data. output enable oe description 0 all output data ports are enabled. 1 all output data ports are in high impedance state.
521 - 33 - 04 6 fig. 3 frequency response of luminance interpolation filter (sampling at ?s=27mhz) fig. 5 frequency response of chrominance interpolation filter (sampling at ?s=27mhz) fig. 7 sin x/x compensation filter frequency response (sampling at ?s=27mhz) fig. 4 frequency response of luminance interpolation filter (sampling at ?s=27mhz) fig. 6 frequency response of chrominance interpolation filter (sampling at ?s=27mhz) 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 -80 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 frequency (mhz) magnitude (db) 0 -4 -8 -12 -16 -20 -24 -28 -32 -36 -40 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 frequency (mhz) magnitude (db) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 0.00 1.35 2.70 4.05 5.40 6.75 8.10 9.45 10.80 12.15 13.50 frequency (mhz) magnitude (db) parameter luminance filter chrominance filter filter order 31 15 pass band ripple +0.038 / -0.025 db (0.0 ?s to 0.21 ?s) +0.2 / -0.2 db (0.0 ?s to 0.21 ?s) dc gain 0.0 db 0.0 db attenuation -6.00 db (at ? s /4) -6.00 db (at ? s /8) stop band attenuation -47 db (0.30 ?s to 0.50 ?s) -28 db (0.17 ?s to 0.50 ?s) fig. 8 luminance and chrominance filter characteristics 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 1.35 2.70 4.05 5.40 6.75 frequency (mhz) magnitude (db) 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0.00 0.54 1.08 1.62 2.16 2.70 3.24 frequency (mhz) magnitude (db)
521 - 33 - 04 7 fig. 9 operation of sync control signal absolute maximum ratings parameter value supply voltage -0.3 to +7.0 v input voltage range (any input) +0.5 to (v dd +0.5) v operating temperature range 0c t a 70c storage temperature range -65c t s 150c lead temperature range (soldering 10 seconds) 260c electrical characteristics v dd = 5v, t a = 0c, r l = 150 w to gnd and 144 w ac coupled unless otherwise shown. parameter symbol conditions min typ max units supply voltage v dd 4.75 5 5.25 v supply current quiescent i ddq v dd = max, v in = 0v - 5 9 ma supply current unloaded i ddu v dd = max, oe = v dd , ? = 27mhz - 85 150 ma input voltage, logic low v il - - 0.2v dd v input voltage, logic high v ih 0.7v dd --v switching threshold v t cmos - 2.5 - v input current: (cmos inputs) i in v in = v dd or gnd -10 1 10 a inputs with pulldown resistors v in = v dd 35 115 222 a inputs with pullup resistors v in = gnd -35 -115 -214 a output voltage, logic low v ol v dd = min, i ol = 4ma - 0.2 0.4 v output voltage, logic high v oh v dd = min, i oh = -4ma 2.4 4.5 - v hi-z output leakage current i oz v dd = max, oe = 1 -10 1 10 a short circuit output current i os v dd = max, output high one pin to ground, one second duration max - - 140 ma input capacitance c in t a = 25c, ? = 1mhz - - 10 pf output capacitance c out t a = 25c, ? = 1mhz - - 10 pf 01234567 clock t pwh t pwl t s t h sync y c b y c r c r y c b si 9..0 t cy
521 - 33 - 04 8 fig. 10 operation of setup control signal fig. 11 input/output timing, bypass = 1 switching characteristics t a from 0c to 70c unless otherwise specified. name parameter test conditions min typ max units t d output delay v dd = min, c l = 25pf 8 9 10 ns t oh output hold time v dd = max, c l = 25pf 1 - - ns t en output enable v dd = min, c l = 25pf - - 8 ns t dis output disable v dd = min, c l = 25pf - - 8 ns t cy cycle time 25 - - ns t pwl clock pulse width low 10 - - ns t pwh clock pulse width high 10 - - ns t s input setup time 8 - - ns t h input hold time 1 - - ns y c b y c r y c b y 01234567 clock t pwh t pwl t s t h setup si 9..0 t cy 01234567 clock t pwh t pwl t s t h t d sync 25 26 27 28 29 30 31 32 clock soa 9 .. 0 sob 9 .. 0 soc 9 .. 0 1 2 3 4 5 6 7 8 y c b y c r c r y c b t oh si 9..0 t cy
521 - 33 - 04 9 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited centaur house, ancells bus. park, ancells rd, fleet, hants, england gu13 8uj tel. +44 (0)1252 761 039 fax +44 (0)1252 761 114 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright march 1995 gennum corporation. all rights reserved. printed in canada. fig. 12 input/output timing, bypass = 0 t pwh t pwl oe 23 24 25 26 27 28 29 30 t s t h t d sync clock y c b y c r c r y c b t oh 01234567 clock 1234 5 soa 9..0 sob 9..0 soc 9..0 t dis t en si 9..0 t cy 6 7 8 revision notes: document identification data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation
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